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Pipeline ADC
Current-Steering DAC

Sigma-Delta CODEC

  Pipeline ADC  
What is the pipeline ADC
The pipelined analog-to-digital converter(ADC) has become the most popular ADC architecture. Lower-sampling-rate applications are still the domain of the successive approximation register(SAR) and integrating architectures (and more recently oversampling/sigma-delta ADCs), whereas the highest sampling rates (a few hundred MS/s or higher) are still obtained using flash ADCs and their variants. However, it is safe to say that pipelined ADCs of various froms have improved greatly in speed, resolution, dynamic performance, and low power in recent years, Because pipeline ADC provide an optimum balance of size, speed, resolution, power dissipation, and analog design effort, it has become increasingly attractive to major data-converter manufacturers and circuit designers. Also known as sub-ranging quantizers, pipeline ADC consists of numerous consecutive stages, each containing a track/hold(T/H), a low-resolution ADC and DAC, and a summing circuit that includes an inter-stage amplifier to provide gain.

Fast and accurate N-bit conversions can be accomplished using at least two or more steps of subranging (also called pipelining). A coarse, M-bit A/D conversion is executed first. Then, using a DAC with at least N-bit accuracy, the result is converted back to one of 2M analog levels and compared with the input. Finally, the difference is converted with a "fine" K-bit flash converter and the two (or more) output stages are combined. The following inequality should be met to correct for overlapping errors:
L M+K > N
where L is the number of stages (depends on the manufacturer), M is the coarse resolution of subsequent stages in the ADC/MDAC circuit, K is the fine resolution of the final ADC stage, and N is the pipeline ADC's overall resolution. Most pipeline ADCs include digital error-correction circuitry that operates between the stages.
Some pipeline quantizers feature a calibration unit that compensates for unwanted side effects such as temperature drift or capacitor mismatch in the multiplying DAC. This digital calibration is usually performed for several (not all) of the pipeline's consecutive stages, using two adjacent codes that cause a transition equal to VREF at the MDAC output. Any deviation from this ideal step is an error that can be measured. When all errors have been acquired and accumulated by the subsequent converter stages, they are stored in an on-board memory. Then the results are fetched from RAM during normal operation to redeem gain and capacitor mismatches in the MDAC stages of the pipeline.
The pipeline ADC is suitable for applications where a relatively high bandwidth and a high resolution are required. Target applications for pipeline ADCs include communication systems, in which total harmonic distortion (THD), spurious-free dynamic range (SFDR), and other frequency-domain specifications are significant; CCD-based imaging systems, in which favorable time-domain specifications for noise, bandwidth, and fast transient response guarantee quick settling; and data-acquisition systems, in which time- and frequency-domain characteristics are both important (i.e., low spurs and high input bandwidth).

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